Case Studies: MIPS, ARM, x86, M68000, and HP 3000

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Case Studies: MIPS, ARM, x86, M68000, and HP 3000 P. A. Wilsey Univ of Cincinnati 1/21. Examples Studied 1.MIPS: modern load/store architecture; principle
Case Studies: MIPS, ARM, x86, M68000, and HP 3000 P. A. Wilsey Univ of Cincinnati

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Examples Studied

1. MIPS: modern load/store architecture; principle architecture of textbook. 2. ARM: modern load/store architecture; low power, commercially successful. 3. X86: old style general register architecture. 4. Motorola 6800: old style general register architecture; orghogonal opcode/operand encoding; once commercially successful. 5. HP 3000: old style stack architecture (mini-computer); logically separates program and instruction spaces.

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MIPS Basic Characteristics I

load/store architecture

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32-bit/64-bit wordsize (discussing 32-bit versions here)

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32-bit program counter (PC)

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32 32-bit general purpose registers

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32 32-bit ft pt registers located in floating-point coprocessor

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word and byte addressable (word operands must be aligned)

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32-bit status register (Figure B.7.1)

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2 operating modes: user and privileged

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big (word 0 ≡ byte 0) or little (word 0 ≡ byte n) endian support

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memory mapped I/O 3 / 21

Instruction Format 6 bits op op op

5 bits rs rs

5 bits 5 bits 5 bits 6 bits rt rd shamt funct rt address/immediate absolute address

ALL instrs are 32 bits long Arith instr format Transfer, branch, immediate Jump instructions

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shamt: shift amount

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funct: additional info to distinguish operation

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register indirect jumps availble

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no separate integer condition codes, branches hold operands to test

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delayed branching with pc relative branching

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The CPU Registers I

R0 always holds the value zero

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Technically available for general use By convention, usage setup as:

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R1, R26, and R27: reserved for the assembler and operation systems R2, R3: used for return values R4-R7: used for the first four arguments to subroutines R8-R15, R24, R25: general use, contents preserved by called environment R16-R23: general use, contents preserved by calling environment R28: points to the middle of a 64K memory block used to hold static data R29: stack pointer R30: frame pointer R31: return address 5 / 21

Exceptions

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all exceptions trap to address 0x80000180 (where the execption handler is assumed to reside)

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32-bit cause register (Figure B.7.2), holds cause of exception

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instructions mfc0/mfc1 and mtc0/mtc1 move from/to control processor (which contains info on the exception)

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The ARM Basic Characteristics I I I I I I I I I I

load/store architecture 32-bit wordsize word and byte addressable (word operands must be aligned) 32-bit status register 6 different operating modes: User, FIQ, IRQ, Supervisor, Abort, and Undefined 16 32-bit general purpose registers (R15 is the PC) banked registers (some have alternates in each operating mode) big or little endian support (set by external pin) conditional execution of instructions instructions can conditionally set condition codes

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Instruction Format

31

27

Cond

19 Opcode

15 Rn

11 Rd

3 Other

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offset summed with Rn

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offset is specified as an immediate or as a register

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register ofset values can be shifted right/left before summing

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offsets store magnitude only

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offset direction held in opcode

0 Rm

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Status Register (CPSR) 31302928

Condition Codes N, Z, C, V

7 6

4

0

Processor Mode Bits Interrupt disable bits (FIQ, IRQ)

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condition codes conditionally set (selected by instr bit (Figure B.2)

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banked for each operating mode

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Operating Modes: User, FIQ, IRQ, Supervisor, Abort, and Undefined

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Banked Registers USER

FIQ

IRQ

Supervisor

Abort

Undefined

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 CPSR

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x86 Basic Characteristics I I I I I I I

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general register architecture 16-/32-/64-bit wordsize (discussing 32-bit versions here) numerous extensions/additions over the years first released in 1978; 8086, 16-bit, based on 8008 8086: registers dedicated to specific purposes 8087: adds ft pt w/ stack 80386 (1985): registers extended to 32-bits, 8 general purpose; primarily 2-address, variable length instructions (lengths of 1-15 bytes), complex instr encoding Pentium/Pentium Pro add MMX (SIMD) instructions (1997) some instructions have different behaviors in real/protected mode 3 operating modes: real, protected, virtual condition codes 11 / 21

The Motorola 68000

Basic Characteristics I

general register architecture

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32-bit internal data path

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16-bit external data path

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word accesses on word addresses only

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big-endian address alignment (word 0 ≡ byte 0)

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terminology: word 16-bits; longword 32-bits

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The Register Structure

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32-bit PC

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8 32-bit data registers D0–D7

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8 32-bit address registers A0–A7 I

A7 is a stack register

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A7 is really 2 distinct registers; one for user mode & one for supervisor mode

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Instructions

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full compliment of addressing modes

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opcode/operands are orthogonal

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e.g., ADD instruction:

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Branching

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Short form:

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Long form:

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The HP 3000: A Stack Based Processor

Basic Characteristics I I I I I

stack in MM (some H/W buffers) 16-bit wordsize 16-bit address bus one 16-bit index register one 16-bit status register

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The Memory Structure I I

logically separate program/data spaces program space has 3 associated CPU registers I I I

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PB: program base, program starting point PL: program limit, end of program PC: program counter

data space divided into 2 parts: the stack area and the data area. data space has 5 associated CPU registers I I I I I

DB: data base, indicates start of stack SP: stack pointer SL: stack limit, bounds the total stack size DL: data limit limit, bounds on the static data area Q: stack marker (activation record)

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The Program and Data Spaces

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The Q Register

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Instructions

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instruction format I

16-bit length typical memory instruction (Load/Store)

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typical stack instruction

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Addressing Modes

Mode PC+ PCDB+ Q+ QSP-

bits 9-0 00dddddddd 01dddddddd 10dddddddd 110ddddddd 1110dddddd 1111dddddd

Effective Addr [PC]+dddddddd [PC]-dddddddd [DB]+dddddddd [Q]+ddddddd [Q]-dddddd [SP]-dddddd

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