Intel x86 Memory Architecture

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Intel x86 Memory Architecture. 2-Level Page Table. 4KB Page Size. 32 bit addresses. PDE/PTE of 32 bits. Virtual Address Format. 12 Bits. Page Offset.
Intel x86 Memory Architecture

2-Level Page Table 4KB Page Size 32 bit addresses PDE/PTE of 32 bits

10 Bits

Virtual Address Format 10 Bits

12 Bits

PDE Num

PTE Num

Page Offset

PDE/PTE Fromat 20 Bits Physical Frame Num

11 Bits

1 Bit

Prot, Mod, Ref Valid

Translation PTBR 0x1000

Describe the result of accessing the following virtual addresses:

0x0 0x1001 0x5001 0x8001 0x0

1024

0x0

0 1 2 3 4

0x0 0x4e001 0x67001 0x20001 0x0



(222 == 0x400000, 212 == 0x1000)

0 1 2 3 4



0x0 0x00803024 0x00c00136

Page Directory (Phys Addr 0x1000)

Page Table (Phys Addr 0x5000)

1024

0x0

Page Table (Phys Addr 0x8000) 0

0x9000

1 2 3 4

0x326001 0x4f001 0x0 0x0



Answers: fault, 0x00020024, fault 1024

0x0

Translation PTBR 0x1000

What is the data stored at virtual address 0x00402004?

Page Directory (Phys Addr 0x1000) 0x0 0x1001 0x5001 0x8001 0x0

… 1024

Answer: 0x0004e001

0x0

0 1 2 3 4

0x0 0x4e001 0x67001 0x20001 0x0



0 1 2 3 4

Page Table (Phys Addr 0x5000)

1024

0x0

Page Table (Phys Addr 0x8000) 0

0x9000

1 2 3 4

0x326001 0x4f001 0x0 0x0

… 1024

0x0

Translation PTBR 0x1000

0 1 2 3 4

0x0 0x1001 0x5001 0x8001 0x0

… 1024

0x0

0x0 0x4e001 0x67001 0x20001 0x0

1024

0x0

Page Table (Phys Addr 0x8000) 0

0x9000

1 2 3 4

0x326001 0x4f001 0x0 0x0



Answers: 0x1000, 0x5000, 0x8000, 0x326000, 0x4f000, 0x200000, x67000, 0x4e000. Ignoring kernel/user bits and write protection, the page tables have been made accessable to the address space (virtual addresses 0x00400000-0x004ffffff), so a process running in this address space could map-in any physical frame it wanted to.

Page Directory (Phys Addr 0x1000)

0 1 2 3 4



List the physical frames that this address space has direct access to. Is this address space properly isolated from accessing any other frames?

Page Table (Phys Addr 0x5000)

1024

0x0

TLB Hit Rates Consider a x86 program consisting of 33% load/store instructions. How many extra memory accesses per instruction executed does this program need when the TLB has a 0%, 95%, or 100% hit rate? Answers: 1.33 base memory accesses per instruction, 100%=0 extra, 0%=2.66 extra, 95%=0.05*2.66 extra

TLB Hit Rates

Derive a formula for and draw a graph of the access time for loads vs the TLB hit rate from 0-100%.

8 Effective Access Time (ns)

L1 cache hit: 1ns L1 cache miss: 8ns TLB cache hit: 0ns L1 hit rate (PDEs/PTEs): 75% L1 hit rate (data): 90%

EAT=PhitTmiss+(1-Phit)Tmiss

(1.7+((1-x)*5.50))

7 6 5 4 3 2 1 0

0.2

0.4 0.6 TLB Hit Rate

0.8

1

TLB Hit Rates L1 cache hit: 1ns L1 cache miss: 8ns TLB cache hit: 0ns L1 hit rate (PDEs/PTEs): 75% L1 hit rate (data): 90% Derive a formula for and draw a graph of the access time for loads vs the TLB hit rate from 0-100%.

EAT=PhitTmiss+(1-Phit)Tmiss

EAT=(0+(1-Ptlbhit)(Ttlbmiss))+ (EATl1) Ttlbmiss=2*(0.75*1+0.25*8) EATl1=0.9*1+0.1*8

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