Project How to step –by step - vlsicad.ucsd.edu

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dc_con --- command dump of DC ... The output is a dc_con.gcf file to use with SE P&R./ 3. ... use the scp copy command ex: scp –r synth out [email protected] ...
Project How to step –by step

1. Synthesis - Synopsys Design Compiler

Files for synthesis files: aes_cores_ 2x_top.v synth_aes_cores_2x.scr

Synthesized results output: aes_cores_ 2x_top.sv --- synthesized Verilog netlist dc_con --- command dump of DC directives

2. Pearl DC to GCF conversion – Cadence Pearl timing analyzer

1. login to asic.ucsd.edu 2. copy dc_con from out directory to /synth 3. move to /synth directory 4. modify pearl.cmd to your Verilog netlist name ex:

set dc_shell_ignored_command_list { set_dont_touch set_dont_touch_network set_local_link_library }

#operating conditions of the slow library set_operating_conditions -process 1 -voltage 1.68 -temperature 125 ReadVerilog aes_cipher_cores_top_2_ps.v TopLevelCell aes_cipher_cores_top_2 #edit this file for .tlf path if necessary #this file reference ReadTLF /home/cichy/public/TSMC18/artisan/2002.8/aci/sc/tlf/slow.tlf

read_dc_script dc_con write_gcf dc_con.gcf quit

5. The output is a dc_con.gcf file to use with SE P&R./

3. Place and Route - Silicon Ensemble

1. Copy /synth and /out folder back to ieng9 machines 2. use the scp copy command ex: scp –r synth out [email protected]:~/final/project/aes_core/syn/bin/. 3. start se with sedsm –m=200 & 4. After Verilog is read into the tool do the following: 5. File | Import | Timing library env_type.gcf in aes_core/SE/gcf 6. File | Import | Constraints dc_con.gcf in aes_core/syn/bin/synth 7. Initialize floorplan. 8. Power plan. 9. Place | Cells check timing driven option 10. Place | Filler Cells | Add Place FILL64 first, FILL32, then FILL16, FILL8 , FILL4 and FILL1. 11. When Qplace has finished do: 12. Place | Clock tree generate for constraint choose ctgen.const in aes_core/SE/ctgen 13. Timing driven routing 14. Wroute | Wroute check the timing driven option 15. Parasitic files 16. File |Export | SDF name the file .sdf. 17. Report | RC name the .rspf file.

4. STA - PrimeTime 5. Back Annotion – Primetime , Design Compiler



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